Technologien für Epitaktische Ferroelektrische Perowskittransistoren auf Gepuffertem Silicium

Details

Veröffentlichungs-Nr.

EP4672902

Aktenzeichen

EP25185014

Anmeldetag

24. Juni 2025

Veröffentlichung

4. März 2026

Rechtsraum

EP

IPC

H10D30/67H01L21/02H10D30/01H01L21/285H01L21/768H10D30/69H10D64/68

Abstract

Technologies for epitaxial perovskite ferroelectric transistors on buffered silicon are disclosed. In an illustrative embodiment, a barrier layer of titanium nitride is deposited on a silicon substrate using domain matching epitaxy, which allows the titanium nitride to grow with relatively low stress and a low number of defects, despite a 22% misfit between the lattice constant for titanium nitride and that lattice constant for silicon. The barrier layer prevents silicon monoxide (SiO) from forming when oxides are grown as later layers. In some embodiments, some or all of the titanium nitride barrier layer may be used as a gate electrode for the transistor.

Anmelder

Firma

INTEL Corporation

Land

🇺🇸 USA

Fachgebiete