Adaptive Architektur für Speichernahe Berechnung mit Gemeinsamen Inaktiven Speicherinternen Rechnervorrichtungen

Details

Veröffentlichungs-Nr.

EP4711982

Anmeldetag

28. August 2025

Veröffentlichung

18. März 2026

Rechtsraum

EP

IPC

G06N3/0464, G06N3/063

Abstract

A hardware accelerator includes a plurality of functional circuits, a stream switch, one or more data reshape units coupled to the plurality of functional circuits via the stream switch to stream data to and from functional circuits of the plurality of functional circuits, and one or more In-Memory Computing (IMC) clusters coupled to the stream switch. In operation, inactive IMC devices of at least a subset of the one or more IMC clusters are accessible to at least a subset of the one or more data reshape units, via memory interface independent from the stream switch, to serve as at least part of Tightly-Coupled Memory (TCM) dedicated to at least one of the one or more data reshape units.

Anmelder

Firma

STMicroelectronics International N.V.

Land

🇨🇭 Schweiz