Interruptregisterstapelung in einem Datenverarbeitungssystem
Anmelder: NXP B.V. 🇳🇱
Details
- Veröffentlichungs-Nr.
- EP4715581
- Anmeldetag
- 24. September 2024
- Veröffentlichung
- 25. März 2026
- Rechtsraum
- EP
- IPC
- G06F9/38
Abstract
A processor includes fetch circuitry configured to fetch instructions and a speculation control circuit. The fetch circuitry is configured to, in response to a first interrupt received by the processor, fetch a first interrupt handler instruction for the received first interrupt. The speculation control circuit is configured to, in response to the first interrupt received by the processor, begin speculative pushing of registers onto a memory stack in accordance with a predetermined register order prior to completion of the fetch of the first interrupt handler instruction for the first interrupt, in which a register tracking value is updated with each speculative push.
Anmelder
- Firma
- NXP B.V.
- Land
- 🇳🇱 Niederlande
Niederländischer Halbleiterhersteller mit Sitz in Eindhoven. Entwickelt Chips und Halbleiterlösungen für Automobiltechnik, Kommunikation, Sicherheit sowie industrielle Anwendungen.
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