Schwarzweller, Thomas

A computer implemented method of detecting one or more objects in an image. The method comprises processing a strip of the image, the strip comprising S lines of pixels of the image, with a backbone model to extract backbone features. The backbone features are processed with a neck model to enhance and/or fuse the backbone features and thereby produce neck features. The neck features are processed with a head model to detect one or more objects in the image. The step of processing a strip of the image is repeated until the whole image is processed.

The present disclosure relates to signal generation circuitry that includes first square wave conversion circuitry including a first input and a first output and second square wave conversion circuitry comprising a second input and a second output. The second output is coupled to the first input of the first square wave conversion circuitry, and the square wave conversion circuitry is configured to generate a first square wave based on a first oscillating signal received at the second input. The first square wave and a second oscillating signal are combined to produce a combined signal, and wherein the first square wave conversion circuitry is configured to generate a second square wave based on the combined signal.

A Frequency Hopping Angular Spread (FHAS) technique senses an environment multiple times using an IR-UWB, a Phase-Modulated Continuous Wave (PMCW), or another modulation scheme, and a carrier signal having a different frequency offset during different intervals and to create an angular spread of reflections in corresponding observations, thereby enabling separation of a reflected signal component from a coupled signal component for enhanced radar capability and accuracy. Embodiments of the FHAS technique generate a collected complex Channel Impulse Response (CIR). Embodiments of the FHAS technique use the angular spread of reflections and the collected complex CIR to separate a reflected signal component from a coupled signal component where the reflected signal component corresponds to a reflection from a static object or a relatively close object, thereby reducing the range of a blind zone in radar and providing capabilities for increasing precision of object distance estimation in a radar system.

A multiple core processing system as described herein for optimizing broadcast operations includes multiple first-level (L1) caches, a distributed second-level (L2) cache system including multiple L2 cache partitions each having a unique identifier, and a routing network that enable communications between the L1 and L2 caches. Each L1 cache sends a request message with a memory address to a targeted L2 cache partition. When rejected, the L1 cache resends the request only in response to a retry message that incorporates an identifier that matches a locally stored identifier. Each L2 cache partition sends a reject message to a requesting L1 cache when busy and later broadcasts a retry message that incorporates its identifier when not busy. The L1 cache predetermines the identifier of the target L2 cache partition when sending the request, or each L2 cache partition incorporates its identifier in the reject message.

Aspects of this disclosure are directed to, DCO circuits and methods. The DCO, comprise: an inductance-capacitance, (LC), resonant circuit having a first branch connected in parallel with a second branch, each branch comprising a capacitor and an inductive-element connected in series with the capacitor; a first transistor connected, by its main terminals, across the capacitor of the first branch; a second transistor connected, by its main terminals, across the capacitor of the second branch; and a biasing current source arranged and connected to provide current to the resonant circuit; wherein a control terminal of the transistor of each branch is connected to a node between the respective capacitor and respective inductive-element of an opposite branch, and wherein at least one of the first transistor and second transistor is controllable to adjust a transconductance of the respective branch.

An apparatus and method for beam steering an antenna array for a MIMO receiver. A signal output and at least one phase shifted output is produced for each antenna element in a MIMO antenna array that receives a phase shift control input, where the at least one phase shifted output is phase shifted relative to the signal output based upon the phase shift control input. A plurality of combined signals is produced for input to a MIMO receiver, where each combined signal is produced for a group of antenna elements and where each respective combined signal includes a combination of: a signal output of a first antenna element and a phase shifted output of at least a second antenna element. A phase shift control input is produced that creates a reduced antenna gain pattern in a direction of a detected strong signal for each respective pair of antenna elements.

There is provided boundary cells arranged to form a boundary between a first power domain and a second power domain. Each power domain has an associated power rail. The boundary cells physically and electrically isolate functional cells of the first power domain from functional cells of the second power domain. Each boundary cell comprises a first well tap having a first conductivity type provided within a first region of a substrate, wherein the first well tap is electrically connected to a ground rail, and a second well tap having a second conductivity type provided within a second region of the substrate, wherein the second well tap is electrically connected to the power rail of the first power domain. The power rails of each power domain extend partially across the boundary cell, the first power rail being physically and electrically isolated from the second power rail.

A data processing system (100) includes a requestor (104), a split transaction interconnect (102), and address mapping circuitry (110). The requestor (104) issues block access requests (1) to a target peripheral (112). The target peripheral (112) includes a set of first-in first-out structures (FIFOs) (130) which buffer incoming or outgoing data. The split transaction interconnect (102) has a requestor port (122) coupled to the requestor (104) and a target port (124) coupled to the target peripheral (112). The target port (124) breaks a single block access request from the requestor into multiple smaller access requests (2) for the target peripheral (112), each including a corresponding access address, in which the corresponding access addresses of the multiple smaller access requests access consecutive address locations of the target peripheral (112). The address mapping circuitry (110) maps (3) each of the corresponding access addresses of the multiple smaller access requests generated from the single block access request access to a same register of a first FIFO (130) of the target peripheral (112).

The disclosure relates to methods of training an object detecting and tracking model. The object detecting or tracking model is trained by receiving (S201) location telemetry data transmitted by an object within the field of view and receiving (S203) sensor data from a sensor and derives object data therefrom. The object detecting and tracking model derives the ground truth from the location telemetry data and uses that to train the model. The disclosure further discusses related systems

The disclosure relates to a frequency doubler circuit (100) comprising: first and second input terminals (101, 102) for receiving an input voltage signal (IN+, IN-) at a first frequency; a first pair of transistors (103a, 103b) connected between a supply line (104) and a first node (105); a second pair of transistors (106a, 106b) connected between a common line (107) and a second node (108), the first and second pairs of transistors (103a, 103b, 106a, 106b) having gates coupled to the respective first and second input terminals (101, 102); an output matching circuit (109) having first and second output terminals (110, 111) for providing an output voltage signal (OUT+, OUT-) at a second frequency; a first common gate transistor (112) connected between the first node (105) and a first input (113) of the output matching circuit (109); and a second common gate transistor (114) connected between the second node (108) and a second input (115) of the output matching circuit (109).