Speichersteuerung mit Schreibpuffer

Details

Veröffentlichungs-Nr.

EP4715614

Anmeldetag

21. August 2025

Veröffentlichung

25. März 2026

Rechtsraum

EP

IPC

G06F13/16, G06F3/06

Abstract

A non-volatile memory (NVM) controller is configured to control reads from and writes to an NVM array, and includes a write buffer and a buffer control circuit. The write buffer includes a plurality of entries, each configured to store a write access having a corresponding page address of the NVM array and corresponding write data. The buffer control circuit is configured to store a write access having a corresponding page address of the NVM array and corresponding write data, and generate burst writes from the write buffer to the NVM array. The buffer control circuit generates a burst write by sequentially selecting write accesses from the write buffer which have consecutive page addresses, in which the length of the burst write is undefined when the burst write to the NVM array is initiated.

Anmelder

Firma

NXP USA, Inc.

Land

🇺🇸 USA