Verbesserte Entfernung von Opfermaterial für Minimierte Kanalerweiterungen

Details

Veröffentlichungs-Nr.

EP4716405

Anmeldetag

2. September 2025

Veröffentlichung

25. März 2026

Rechtsraum

EP

IPC

H10D30/01, H10D30/00

Abstract

Integrated circuit (IC) devices having dielectric spacers between parallel channel structures (e.g., of nanoribbons, nanowires, etc.). A transistor structure may have first and second channel layers between source and drain bodies, a gate stack with a gate metal and gate dielectric between the channel layers, and a dielectric spacer between the channel layers and between the gate dielectric and one of the source and drain bodies. The dielectric spacer may have a significant (or minimal) curvature such that a width of the dielectric spacer between the channel layers is much greater (or not much greater) than widths of the dielectric spacer at the channel layers or than a minimum distance separating the gate metal between the channel layers from one of the source and drain bodies. An added or altered etch may remove sacrificial dummy gate material from between the channel layers and the gate side of the dielectric spacer.

Anmelder

Firma

INTEL Corporation

Land

🇺🇸 USA