Statischer Direktzugriffspeicher mit Schreibhilfe pro Reihe

Details

Veröffentlichungs-Nr.

EP4718455

Anmeldetag

25. Juli 2025

Veröffentlichung

1. April 2026

Rechtsraum

EP

Abstract

Embodiments herein relate to Static Random-Access Memory (SRAM) where a write assist technique is facilitated using power supply lines (Vcc) which extend in a word line direction. The SRAM can be implemented using complementary field-effect transistor (CFET) technology, where n-type and p-type transistors are arranged in a stacked configuration on top and bottom levels, respectively of a stack. In one aspect, a power supply line is shared by a row of adjacent memory cells. In another aspect, a power supply line is shared by a row of memory cells in alternate columns. The configurations avoid disturb of unselected cells due to a Vcc collapse during writing. In another aspect, an eight-transistor SRAM memory cell includes transistor gates to reduce Vmin, the minimum supply voltage at which a memory array can operate without failure.

Anmelder

Firma

INTEL Corporation

Land

🇺🇸 USA