Gestapelter Ferroelektrischer Random-Access-Speicher

Details

Veröffentlichungs-Nr.

EP4718970

Anmeldetag

31. Juli 2025

Veröffentlichung

1. April 2026

Rechtsraum

EP

Abstract

An integrated circuit die includes an array of memory cells between a first surface and a second surface opposite the first surface. A first memory cell proximate the first surface comprises a first capacitor over a first transistor. A second memory cell under the first memory cell comprises a second capacitor under a second transistor. The first transistor may be stacked on the second transistor. The capacitors may include ferroelectric or antiferroelectric materials. The first capacitor is coupled with a first plate line located between the first surface and the array of memory cells. A via couples the second capacitor with a second plate line between the first surface and the array of memory cells.

Anmelder

Firma

INTEL Corporation

Land

🇺🇸 USA