Zellenarchitektur mit Gabelblatt- und Tor-All-Around-Vorrichtungen

Details

Veröffentlichungs-Nr.

EP4718984

Anmeldetag

17. September 2025

Veröffentlichung

1. April 2026

Rechtsraum

EP

Abstract

Techniques are provided herein to form semiconductor devices having cells that include both forksheet devices and GAA devices to increase cell performance. The techniques can be used in any number of integrated circuit applications and are particularly useful with respect to logic and memory cells. The dielectric spine of the forksheet devices extends in a first direction across the cell and also acts as a gate cut between the GAA devices. Accordingly, forksheet devices are formed on one side of the cell while GAA devices are formed on the opposite side of the cell. Semiconductor material from the nanosheets and nanoribbons has a tapering width (along a second direction orthogonal to the first direction) within a transition zone between the different sides of the cell.

Anmelder

Firma

Intel Corporation

Land

🇺🇸 USA