Gabelscheibentransistoren mit Umhülltem Gate-Dielektrikum

Details

Veröffentlichungs-Nr.

EP4718985

Anmeldetag

17. September 2025

Veröffentlichung

1. April 2026

Rechtsraum

EP

Abstract

Techniques are provided to form semiconductor devices that include forksheet transistors with a self-aligned dielectric spine and nanosheets with a wrapped-around gate dielectric. The dielectric spine may be formed prior to the formation of gate structures. In an example, first and second semiconductor devices have first and second semiconductor regions, respectively, extending in a first direction. The first and second semiconductor regions may include any number of nanosheets. A dielectric spine extends in the first direction centrally aligned between the first and second semiconductor regions. The gate dielectric of the gate structures on either side of the dielectric spine is wrapped around the semiconductor regions, such that the gate dielectric is present between the nanosheets and the dielectric spine along the second direction. The dielectric spine may include a dielectric liner that itself is removed prior to formation of the gate structures, thus provided space for the wrapped-around gate dielectric.

Anmelder

Firma

INTEL Corporation

Land

🇺🇸 USA