Halbleiterchip mit Vertikaler Transistorvorrichtung

Details

Veröffentlichungs-Nr.

EP4718989

Anmeldetag

26. September 2024

Veröffentlichung

1. April 2026

Rechtsraum

EP

Abstract

The disclosure relates to a semiconductor die (1) with a semiconductor body (10), the semiconductor die (1) comprising: a vertical transistor device (20) with a first load region (21) and a second load region (22) at opposite sides (10.1, 10.2) of the semiconductor body (10); an additional transistor device (40) with a source region (41) at a first side (10.1) of the semiconductor body (10), a gate trench (45), a body region (47) aside the gate trench (45) and a drain region (42) below the body region (47); an electrical isolation (60) in the semiconductor body (10); a vertical contact element (80) extending from the first side (10.1) into the semiconductor body (10); wherein the electrical isolation (60) is arranged laterally between the vertical transistor device (20) and the additional transistor device (40), and wherein the vertical contact element (80) makes electrical contact to the drain region (42) of the additional transistor device (40) and connects the drain region (42) to the first side (10.1) of the semiconductor body (10).

Anmelder

Firma

Infineon Technologies Austria AG

Land

🇦🇹 Österreich