Gabelfolientransistoren mit Dielektrischem Dorn mit Luftspalt

Details

Veröffentlichungs-Nr.

EP4718992

Anmeldetag

1. August 2025

Veröffentlichung

1. April 2026

Rechtsraum

EP

Abstract

Techniques are provided herein to form semiconductor devices that include forksheet transistors with a self-aligned dielectric spine having an airgap. The airgap may constitute a majority of the total volume of the dielectric spine, this lowering the dielectric constant of the dielectric spine and decreasing parasitic capacitance. In an example, first and second semiconductor devices have first and second semiconductor regions, respectively, extending in a first direction between corresponding source and drain regions. The first and second semiconductor regions may include any number of nanosheets. A dielectric spine extends in the first direction between the first and second semiconductor regions. The dielectric spine includes a dielectric liner adjacent to the sides of the first and second semiconductor regions. A remaining volume of the dielectric spine at least partially bound by the dielectric liner includes an airgap. A dielectric cap structure may be included over the airgap.

Anmelder

Firma

INTEL Corporation

Land

🇺🇸 USA