Herstellung von Integrierten Gate-All-Around-Schaltungsstrukturen mit Skalierung Strukturierter Nanodrähte

Details

Veröffentlichungs-Nr.

EP4718995

Anmeldetag

17. September 2025

Veröffentlichung

1. April 2026

Rechtsraum

EP

Abstract

Integrated circuit structures having patterned nanowire thickness scaling are described. For example, a structure includes a first device of a device type including a first vertical arrangement of horizontal nanowires, and a first gate stack having a first conductive layer over a first gate dielectric layer. A second device of the device type includes a second vertical arrangement of horizontal nanowires laterally spaced apart from the first vertical arrangement of horizontal nanowires, and a second gate stack having a second conductive layer over a second gate dielectric layer. Each of the nanowires of the second vertical arrangement of nanowires has a vertical thickness less than a vertical thickness of each of the nanowires of the first vertical arrangement of horizontal nanowires. The nanowires of the second vertical arrangement of nanowires have a vertical spacing greater than a vertical spacing of the nanowires of the first vertical arrangement of horizontal nanowires.

Anmelder

Firma

INTEL Corporation

Land

🇺🇸 USA