Geteilte Verarbeitung von Integrierten Schaltungsschichten mit Hochgenauer Verbindung

Details

Veröffentlichungs-Nr.

EP4719028

Anmeldetag

16. September 2025

Veröffentlichung

1. April 2026

Rechtsraum

EP

Abstract

Split processing of integrated circuit layers with high accuracy bonding is described. In an example, an integrated circuit structure includes a front-end-of-line (FEOL) stack having an uppermost surface including first conductive features and first dielectric features. A back-end-of-line (BEOL) stack is above the FEOL stack. The BEOL stack has a bottommost surface including second conductive features and second dielectric features in contact with corresponding ones of the first conductive features and first dielectric features of the uppermost surface of the FEOL stack, respectively. The second conductive features are laterally offset from the corresponding first conductive features.

Anmelder

Firma

Intel Corporation

Land

🇺🇸 USA