Halbleitergehäuse und Halbleitergehäuseanordnung

Details

Veröffentlichungs-Nr.

EP4719035

Anmeldetag

3. September 2025

Veröffentlichung

1. April 2026

Rechtsraum

EP

Abstract

A semiconductor package and a semiconductor package assembly are provided. The semiconductor package includes an interconnect structure, a chip, a redistribution layer (RDL), a molding compound, and through mold vias (TMVs). The chip is arranged on and coupled to the interconnect structure. The RDL is arranged on and coupled to the chip. The molding compound is arranged on the interconnect structure and encapsulates the chip and the RDL. The TMVs pass through the molding compound and are connected between the RDL and the interconnect structure. The chip includes a back-side connect structure, a transistor layer, a front-side connect structure and a carrier. The back-side connect structure is connected to the interconnect structure. The transistor layer is located on the back-side connect structure. The front-side connect structure is located on the transistor layer. The first carrier is located on and coupled to the interconnect structure.

Anmelder

Firma

MEDIATEK INC.

Land

🇹🇼 Taiwan