Eingangsfilterstufe für Verarbeitungseinheit in einem Hardwarebeschleuniger

Details

Veröffentlichungs-Nr.

EP4722934

Anmeldetag

24. September 2025

Veröffentlichung

8. April 2026

Rechtsraum

EP

IPC

G06F15/173, G06F13/28

Abstract

An input filtering stage for a processing unit in a hardware accelerator is disclosed. A hardware accelerator includes one or more processing units. Each of the one or more processing units includes a buffer and an input filtering stage. The input filtering stage is configured to receive an input data stream that includes a plurality of input channels. Data selection criteria that indicate one or more input channels of the plurality of input channels are obtained. The one or more input channels from the plurality of input channels are selected based on the data selection criteria and provided to the buffer.

Anmelder

Firma

STMicroelectronics International N.V.

Land

🇨🇭 Schweiz