Adaptive Pufferteilung in Rekonfigurierbaren Multikern-Streaming-Basierten Architekturen

Details

Veröffentlichungs-Nr.

EP4722986

Anmeldetag

22. September 2025

Veröffentlichung

8. April 2026

Rechtsraum

EP

IPC

G06N3/063

Abstract

A hardware accelerator includes a plurality of functional circuits, a stream switch, and a plurality of neural network processing cores coupled to the plurality of functional circuits via the stream switch to stream data to and from functional circuits of the plurality of functional circuits, wherein the neural network processing cores include at least one sender core having a buffer whose buffer content is sharable with at least one receiver core of the neural network processing cores via at least one of a dedicated output stream link or dedicated virtual channel on a pre-existing output stream link, and wherein the at least one of the dedicated output stream link or dedicated virtual channel is dedicated to sharing the buffer content via the stream switch.

Anmelder

Firma

STMicroelectronics International N.V.

Land

🇨🇭 Schweiz