Sar-Pipeline-Analog-Digital-Wandler (adc) mit Vordergrundselbstkalibrierung
Anmelder: NXP USA, Inc. 🇺🇸
Details
- Veröffentlichungs-Nr.
- EP4723483
- Anmeldetag
- 26. September 2025
- Veröffentlichung
- 8. April 2026
- Rechtsraum
- EP
Abstract
A pipelined SAR ADC that is connected to receive an analog input voltage includes a first ADC stage, a residue amplifier, a second ADC stage, and calibration circuitry coupled and configured to add first and second ADC conversion results to form an uncalibrated digital value, and to apply calibration values to the uncalibrated digital value to obtain a calibrated digital value corresponding to a calibrated digital representation of the analog input voltage, where the calibration values include a first ADC stage DAC element mismatch calibration value corresponding to the first ADC conversion result, an offset calibration value, and a gain adjustment factor.
Anmelder
- Firma
- NXP USA, Inc.
- Land
- 🇺🇸 USA
US-amerikanische Gesellschaft des Halbleiterkonzerns NXP, die Chips und Halbleiterlösungen für Automobiltechnik, Kommunikation und Industrieelektronik entwickelt.
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