Speichersteuerung mit Überabtastungsspeicher-E/a

Details

Veröffentlichungs-Nr.

EP4726721

Anmeldetag

2. Oktober 2025

Veröffentlichung

15. April 2026

Rechtsraum

EP

IPC

G11C7/10, G06F13/16, H04L25/49

Abstract

A memory controller in an integrated circuit system includes a receiver circuit that performs oversampling in time and voltage. The receiver circuit receives a data signal modulated with pulse amplitude modulation (PAM) having N signal levels from a memory module over a data lane, N > 2. The receiver circuit generates K samples by sampling the data signal at a sequence of time points in a unit time interval. The receiver circuit uses R voltage comparator blocks to generate R signal level estimates from the same sample out of the K samples. The voltage comparator blocks compare the same sample against (N-1) voltage thresholds with different offsets configured for different voltage comparator blocks. The receiver circuit identifies one of the N signal levels to which the data signal is mapped based on all signal level estimates generated from the K samples, and outputs a symbol corresponding to the identified signal level.

Anmelder

Firma

MEDIATEK INC.

Land

🇹🇼 Taiwan