Systeme und Verfahren zur Gleichzeitigen Decodierung von Produkt-Elevierten Low-Density Parity Check (ldpc)-Codes

Details

Veröffentlichungs-Nr.

EP4727019

Anmeldetag

8. Oktober 2025

Veröffentlichung

15. April 2026

Rechtsraum

EP

IPC

H03M13/11, H03M13/00(RICHARDSON TOM et al.)

Abstract

In some implementations, an apparatus may include a receiver and on or more processors. The one or more processors may be configured to identify a low-density parity-check (LDPC) code corresponding to a bipartite graph comprising a set of edges connected between a first set of nodes and a second set of nodes. The one or more processors may be configured to generate a first set of messages and a second set of messages using the encoded data. The one or more processors may be configured to communicate the first set of messages with the first subset and the second set of messages with the second subset, concurrently using the bipartite graph. The one or more processors may be configured to identify decoded data based at least on processing of the first set of messages and the second set of messages.

Anmelder

Firma

Avago Technologies International Sales Pte. Limited

Land

🇸🇬 Singapur