Dilg, Haeusler, Schindelmann Patentanwaltsgesellschaft mbH

A data plane of a network switch can include: a packet switch including a first port and a second port; a first processor, coupled to the packet switch and a control plane, the first processor comprising: a first digital circuit configured to: receive a first payload of a first packet ingress to the first port; and convert first numerical data in the first payload from a first format to a second format; and a second digital circuit configured to: receive the first numerical data from the first digital circuit and second numerical data; and perform a first compute operation with the first and second numerical data as input; wherein the first processor is configured to return a second packet to the packet switch for egress from the second port, a second payload of the second packet including numerical data that results at least in part from the first compute operation.

In some implementations, a wireless device may include one or more processors. The one or more processors may be configured to perform first soft demapping using sphere decoding on first data relating to a first stream and a second stream among a plurality of spatial streams. The one or more processors may be configured to perform second soft demapping using sphere decoding on second data relating to the first stream and the second stream, different from the first data. The one or more processors may be configured to determine, using a result of the first soft decoding and a result of the second soft decoding, log likelihood ratio (LLR) values of the first stream and the second stream.

There is described a component carrier (100) and a method of manufacturing a component carrier. The component carrier comprises: at least one electrically insulating layer structure (106) and at least one electrically conductive layer structure (104); wherein said at least one insulating layer structure (106) comprises at least one opening (108) which connects a main surface (101) of the at least one electrically insulating layer structure (106) with at least part of the at least one electrically conductive layer structure (104), said at least one opening (108) being delimited by a lateral wall (109), said lateral wall (109) comprising two portions, a first portion (109a) and a second portion (109b), one above the other in a thickness direction of the at least one insulating layer structure (106), wherein said two portions (109a, 109b) have a different extension one to each other in the thickness direction of the at least one insulating layer structure (106).

The present invention describes a component carrier (100) and and a method of manufacturing a component carrier. The component carrier comprises a stack (101) with at least one electrically conductive layer structure (102) and a plurality of electrically insulating layer structures. An outermost electrically insulating layer structure (103) of the plurality of electrically insulating layer structures comprises sections (201, 202) with a plurality of openings (105), said sections (201, 202) corresponding to several planar positions at said outermost electrically insulating layer structure (103). Each opening (105) exposes a conductive portion (106) associated to the least one electrically conductive layer structure (102), wherein each opening (105) has a lateral wall (107) defining the circumference of the respective opening (105). The circumference of each opening (105) has a symmetry axis (108) being perpendicular to a main surface (109) of the electrically conductive layer structure (102).

In some implementations, an apparatus may include a receiver, a plurality of circuits, and on or more processors. The plurality of circuits may include a same set of input/output (I/O) interfaces and performing a respective function of processing data at the PHY layer or the MAC layer. The one or more processors may be configured to select a first set of circuits of the plurality of circuits to use as a first datapath to process, through each of the first set of circuits, data received by the receiver. Each of the first set of circuits can be configured to communicate with another one of the first set of circuits using the same set of I/O interfaces and perform the respective function of processing the data.

There is provided a component carrier and method for manufacturing the same. The component carrier comprises a stack having a plurality of electrically insulating layer structures and at least one electrically conductive layer structure, and at least one electrically vertical connection encapsulated by a first dielectric material of a first electrically insulating layer structure of the plurality of electrically insulating layer structures, wherein the at least one electrically vertical connection comprises at least one pad and at least one pillar vertically connected to each other.

In some implementations, a device may one or more processors. The one or more processors may be configured to perform soft demapping using sphere decoding in multiple input multiple output (MIMO) systems and using different modulation sizes in unequal quadrature amplitude modulation (QAM) across a plurality of spatial streams.

The present invention describes a component carrier (100) comprising a stack with a plurality of electrically insulating layer structures, wherein a first one (101) of the plurality of electrically insulating layer structures comprising a through hole (104) passing from a first main surface (105) to an opposed second main surface (106) of the first electrically insulating layer structure (101). A second one (102) of the plurality of electrically insulating layer structures comprises fillers (111) embedded therein, wherein the second electrically insulating layer structure (102) comprises a third main surface (107) in contact with the first main surface (105) of the first electrically insulating layer structure (101), closing the through hole (104), and comprises a fourth main surface (108) opposed to the third main surface (107). The second electrically insulating layer structure (102) comprises a cover portion (109) and a surrounding portion (110), wherein the cover portion (109) overlaps the through hole (104). The fillers (111) in the surrounding portion (110) are closer to the fourth main surface (108) than the fillers (111) in the cover portion (109).

Example methods and systems for attribute-based probabilistic filter configuration for key-value lookup handling are described. In one example, a computer system may maintain a first probabilistic filter that represents a first set of keys for handling first key-value lookups during a first time period. The computer system may generate lookup attribute information to track one or more attributes associated with the first key-value lookups during the first time period. Based on the lookup attribute information, the computer system may select a second set of keys. The computer system may configure the first probabilistic filter or a second probabilistic filter to represent the selected second set of keys for handling second key-value lookups during a second time period.

In an embodiment, a transistor has a semiconductor layer with a first-type region and a second-type region adjacent to the first-type region. An insulating structure extends into the second-type region. A first conductor is on the first-type region. A second conductor is on the second-type region. A first gate structure is on the semiconductor layer between the first and second conductor. The first gate structure includes semiconductive layers that are vertically spaced from each other and a first gate metal that contacts the semiconductive layers. A second gate structure is on the semiconductor layer between the first gate structure and the second conductor. The second gate structure includes semiconductive layers that are vertically spaced from each other. The second gate structure further includes a second gate metal that contacts the semiconductive layers of the second gate structure.