Hochauflösender Zeit-Digital-Wandler mit Grossem Bereich

Details

Veröffentlichungs-Nr.

EP4733862

Anmeldetag

21. Oktober 2025

Veröffentlichung

29. April 2026

Rechtsraum

EP

IPC

G04F10/00

Abstract

A time to digital converter including multiple delay lines and an output adder. Each delay line includes multiple series-coupled buffers receiving a start signal, multiple latches each having an input coupled to an output of a buffer and an output providing one of multiple binary values in response to a stop signal, and an adder. Each adder adds the binary values from corresponding latches in response to the stop signal and provides a corresponding one of multiple digital output values. The output adder adds the digital output values from the delay lines and provides a digital output value indicative of a measured delay. The start and stop signals may be buffered to provide multiple start and stop signals each provided one of the delay lines. Each start signal may be delayed by one of multiple different delays. Select logic may combine multiple delay lines into a longer delay line group.

Anmelder

Firma

NXP USA, Inc.

Land

🇺🇸 USA