Erkennung von Speichergefahren in Massiv Parallelen und Verteilten Systemen

Details

Veröffentlichungs-Nr.

EP4733940

Anmeldetag

17. Oktober 2025

Veröffentlichung

29. April 2026

Rechtsraum

EP

IPC

G06F11/07, G06F11/30

Abstract

Systems and methods are provided for detecting memory hazards in memory, such as in massively parallel and distributed systems. In examples, a memory hazard logic detects access of a memory by a device communicatively coupled to the memory. The memory hazard logic identifies a memory access type and a memory address range being accessed, based on information obtained when monitoring a memory access transaction between the device and the memory. The memory hazard logic determines whether the memory access type on the memory address range is subject to memory access rules contained in a rules table. If so, the memory hazard logic determines whether the memory access type matches a memory access rule associated with each memory address in the memory address range. For each such memory address, the memory hazard logic notifies the device regarding a memory hazard triggered by the memory access transaction.

Anmelder

Firma

Microsoft Technology Licensing, LLC

Land

🇺🇸 USA