Halbleiteranordnung

Details

Veröffentlichungs-Nr.

EP4734112

Anmeldetag

16. Juli 2025

Veröffentlichung

29. April 2026

Rechtsraum

EP

Abstract

A memory device includes: a first memory die (51) including a first monitoring pad connected to a monitoring line (ML1), and a first current monitoring logic configured to output a first current monitoring signal to the first monitoring pad; and a second memory die (52) including a second monitoring pad connected to the monitoring line (ML1), and a second current monitoring logic configured to output a second current monitoring signal to the second monitoring pad, wherein the first current monitoring signal includes first current data of N bits, the first current data including a peak value of a consumption current of the first memory die (51), N being a natural number equal to or greater than two, wherein the second current monitoring signal includes second current data of N bits, the second current data including a peak value of a consumption current of the second memory die (52), wherein the first current monitoring logic and the second current monitoring logic are configured to alternately occupy the monitoring line (ML1), and wherein the first current monitoring logic is configured to recover a first clock signal using the second current monitoring signal that is output to the monitoring line (ML1), and the second current monitoring logic is configured to recover a second clock signal using the first current monitoring signal that is output to the monitoring line (ML1).

Anmelder

Firma

SAMSUNG ELECTRONICS CO., LTD.

Land

🇰🇷 Südkorea