Chip-On-Rail-System in einer Verpackung

Details

Veröffentlichungs-Nr.

EP4734743

Anmeldetag

24. Oktober 2025

Veröffentlichung

29. April 2026

Rechtsraum

EP

Abstract

A multi-level interconnect structure is formed on a semiconductor wafer to include conductive power-distribution rail bonding structures which are positioned for mounting on a package substate by forming a patterned insulator layer on the multi-level interconnect structure which includes a defined array of patterned openings, and then forming an array of conductive power-distribution rail bonding structures in the defined array of patterned openings to extend substantially over the top surface of the interconnect structure, where the array of conductive power-distribution rail bonding structures includes a plurality of parallel conductive rails which are aligned in parallel and distributed uniformly to directly electrically connect power over the plurality of conductive interconnect structures to the IC device.

Anmelder

Firma

NXP USA, Inc.

Land

🇺🇸 USA