Colaiuda, Antonella

The present disclosure describes a method and a system for detecting fault injection attacks in a digital signature. The method comprises the steps of: initiating a first counter configured to count a number of generations of digital signature candidates, initiating a second counter configured to count a number of digital signature candidates which fail security checks, incrementing the first counter each time that a digital signature candidate is generated, selecting a size β and parsing the first counter in block intervals of said size β, performing at least one security check on each digital signature candidate generated, incrementing the second counter in response to a digital signature candidate failing at least one security check, and in response to the first counter being an integer multiple of β: assigning to the last completed block interval of said size β a third counter, such third counter configured to count the number of failed security checks in the last completed block interval, assigning to the last completed block interval of said size β a third counter, such third counter configured to count the number of failed security checks in the last completed block interval, comparing the third counter with a criterion based at least on a probabilistic threshold and on said size β. In response to the third counter not fulfilling the criterion the method detects that at least one fault injection attack has been performed.

A packaged device includes a substrate, a die, a die flag, and a plurality of leads. The substrate has a lower surface and an upper surface opposite the lower surface. The die is arranged on the upper surface of the substrate. The die has a lower surface facing the upper surface of the substrate, and an upper surface opposite the lower surface. The die flag includes a cover portion which is arranged over the upper surface of the die. The cover portion has a lower surface and an upper surface opposite the lower surface. The lower surface of the cover portion faces the upper surface of the die. The plurality of leads is arranged around a periphery of the substrate. The plurality of leads includes a first lead connected to the die flag, and a second lead separated from the die flag. Each of the plurality of leads includes an outer portion which has a lower surface and an upper surface opposite the lower surface. The lower surfaces of the plurality of leads are coplanar with and separated from the lower surface of the substrate.

Herein is disclosed a voltage input terminal configured to receive an input voltage; flash analogue to digital converter, ADC; an ADC, wherein the ADC comprises: a plurality of capacitors configured and arranged such that they at least partially define the bit resolution of the ADC; a controller; wherein: the flash ADC is configured to receive the input voltage and provide a flash ADC signal, wherein the flash ADC signal is a digital representation of the input voltage; the controller is configured to provide for pre-charging of the plurality of capacitors based on the flash ADC signal; and after the plurality of capacitors is pre-charged, the controller is configured to provide for sampling of the input voltage onto the plurality of capacitors, and the provision of an ADC output signal comprising a digital representation of the input voltage by the ADC.

The disclosure relates to a Zener diode that is insensitive to external stress, and to a method of making such a Zener diode. A lattice mismatch is used to induce a compressive stress in the junction of the Zener diode in the direction of current flow. The lattice mismatch may be produced by carbon doping.

The present disclosure relates to system and method for generating a digital signature. comprising computing via a hash function a public key; computing a signature comprising an authentication path traversing the node of at least one binary subtree belonging to a hypertree comprising d layers of binary subtrees each comprising a root node and leaf-nodes; storing the leaf-nodes at the top layer d-1, and those of at least one of the binary subtrees at an intermediate layer d-x, where 2≤x<d; extracting a binary subtree index idx_tree and inferring if the extracted binary subtree index idx_tree is associated with at least one binary subtree linked to the stored leaf-nodes at the intermediate layers; choosing an operation mode; generating the digital signature based on the chosen operation mode and on the association of the extracted binary subtree index idx_tree with a binary subtree linked to the stored leaf-nodes at the intermediate layers.

An integrated circuit assembly includes first and second circuit portions, an interposer vertically disposed between the first and second circuit portions, the interposer having a plated through hole with a metallic sidewall, and a metallic pillar that extends through the plated through hole without touching the metallic sidewall. The metallic pillar and the plated through hole together form a vertical coaxial structure constructed and arranged to convey RF (radio frequency) signals between the first and second circuit portions. Embodiments are directed to both the integrated circuit assembly and to a method of manufacturing the integrated circuit assembly.

The present disclosure provides a method of building a UWB network, comprising a plurality of spatially-separated UWB nodes, wherein the plurality of UWB nodes comprises a gateway node and a plurality of non-gateway nodes, the method comprising; identifying at least one gateway-neighbouring node; setting the gateway node into a two-way ranging, TWR, controller mode to provide for transfer of data to each of the identified gateway-neighbouring nodes; for at least a first gateway-neighbouring, FGN, node: identifying, if available, at least one FGN-child node; setting the FGN node into a TWR controller mode to provide for transfer of data to each of the identified FGN-child nodes, wherein the operation of each node in its respective TWR controller mode is non-contemporaneous with the operation of any of its neighbouring nodes in their respective TWR controller mode.

The present disclosure relates to a controller configured to: receive a channel impulse response from a UWB node operating in a radar mode, wherein the UWB node is mounted in a vehicle and directed towards a traversal surface of the vehicle such that the channel impulse response is indicative of reflections of a radar signal from the traversal surface; characterise an irregularity in the traversal surface based on the received channel impulse response and one or more signature channel impulse responses, CIRs, wherein each of the signature CIRs are indicative of an irregularity which may be identified in the CIR of the UWB node.

A method of manufacturing a semiconductor device is provided. The method includes affixing a plurality of semiconductor die on a first major side of a leadframe having a plurality of package sites, each semiconductor die affixed at a respective package site, the leadframe selectively plated such that un-plated regions are formed between the package sites. An encapsulant encapsulates the plurality of semiconductor die and the first major side of the leadframe. A second major side of the leadframe is exposed through the encapsulant. The un-plated regions are etched from the second major side of the leadframe to electrically isolate each package site from one another.

The present specification relates to package semiconductor devices and methods of manufacture thereof. According to a first aspect of the present disclosure, there is provided a packaged semiconductor device comprising a semiconductor die, a first molding compound encapsulating the semiconductor die, a first set of interconnecting solder balls, at least one redistribution layer, such redistribution layer connecting the semiconductor die to the interconnecting solder balls. The packaged semiconductor device further comprises at least one channel extending from the at least one redistribution layer to an exterior of the packaged semiconductor device wherein the at least one redistribution layer comprises pipes coupled to the at least one channel, such pipes transporting steam or moisture or thermal fluids from the at least one channel to the at least one redistribution layer or from the at least one redistribution layer to the at least one channel.