Phasenregelkreisschaltung, Phasenregelverfahren und Frequenzsynthesizer

Details

Veröffentlichungs-Nr.

EP4738709

Anmeldetag

29. Oktober 2025

Veröffentlichung

6. Mai 2026

Rechtsraum

EP

IPC

H03L7/08, H03L7/099, H03L7/18

Abstract

A phase-locked loop circuit, a phase-locking method, and a frequency synthesizer are provided. The phase-locked loop circuit employs phase-rolling clock signal generator component to perform integer frequency division on multiple oscillation clock signals with uniformly varying phases to obtain multiple feedback clock signals with uniformly varying phases; and according to a preset clock cycle, select feedback clock signals with corresponding phase sequences from the multiple feedback clock signals with uniformly varying phases for concatenation, thereby generating the phase-rolling clock signal. This architecture enables fractional-N frequency division phase-locked loop operation. Compared with conventional fractional-N frequency division phase-locked loop implementations using sigma-delta modulator (SDM) circuits, the proposed solution reduces circuit area and power consumption while improving phase-locked loop performance.

Anmelder

Firma

Amlogic (Shanghai) Co., Ltd.

Land

🇨🇳 China

Fachgebiete