Schaltung zur Verriegelung Elektrostatischer Entladungen für Ausgangstreiber

Details

Veröffentlichungs-Nr.

EP4739035

Anmeldetag

7. August 2025

Veröffentlichung

6. Mai 2026

Rechtsraum

EP

Abstract

The present invention provides a circuitry (200) including an output driver (210) and an ESD lock circuit (250). The output driver (210) includes a first transistor (M1) and a second transistor (M2), wherein the first transistor (M1) is coupled between an I/O pad (202) and a ground voltage, and the second transistor (M2) is coupled between the I/O pad (202) and a supply voltage. The ESD lock circuit (250) is coupled between the I/O pad (202) and the ground voltage, and is configured to generate a control signal to control the first transistor (M1) according to a voltage at the I/O pad (202).

Anmelder

Firma

MEDIATEK INC.

Land

🇹🇼 Taiwan