Schaltungen und Verfahren für Direkten Speicherzugriff mit einem Netzwerk auf einem Chip

Details

Veröffentlichungs-Nr.

EP4742050

Anmeldetag

7. Oktober 2025

Veröffentlichung

13. Mai 2026

Rechtsraum

EP

IPC

G06F13/28

Abstract

A configurable integrated circuit includes a network-on-chip and a response buffer circuit coupled to the network-on-chip. The response buffer circuit includes a direct memory access circuit and a controller circuit. The direct memory access circuit generates read requests and write requests to access memory circuits. The controller circuit provides the read requests and the write requests to the memory circuits through the network-on-chip. The controller circuit exchanges data with the memory circuits for the read requests and the write requests.

Anmelder

Firma

Altera Corporation

Land

🇺🇸 USA