Halbleiteranordnung

Details

Veröffentlichungs-Nr.

EP4746633

Anmeldetag

28. Juli 2025

Veröffentlichung

20. Mai 2026

Rechtsraum

EP

Abstract

A semiconductor device includes a back interlayer insulating film (180); a plurality of first channel patterns (NS1) on the back interlayer insulating film (180) and spaced apart from each other in a vertical direction (DR3); a plurality of second channel patterns (NS2) on the back interlayer insulating film (180) and spaced apart from each other in the vertical direction (DR3); a source/drain pattern (160) between the first channel patterns (NS1) and the second channel patterns (NS2); and a source/drain contact (195, 295) connected to the source/drain pattern (160), wherein the source/drain pattern (160) includes a first layer (161) which comes into contact with (162) the first channel patterns (NS1) and the second channel patterns (NS2), a second layer (162) on or below the first layer (161), and a third layer (163) on or above the second layer (162), wherein a width of the first layer (161) in the vertical direction (DR3) decreases and then increases, along a direction from the first channel patterns (NS1) to the second channel patterns (NS2).

Anmelder

Firma

SAMSUNG ELECTRONICS CO., LTD.

Land

🇰🇷 Südkorea