Metall-Gate-Schnitte mit Hohem Aspektverhältnis

Details

Veröffentlichungs-Nr.

EP4750252

Anmeldetag

25. August 2023

Veröffentlichung

27. Mai 2026

Rechtsraum

EP

Abstract

An integrated circuit structure, comprises a first plurality of nanoribbons (104) above a first sub-fin region (108); a second plurality of nanoribbons (104) above a second sub-fin region (108), the second plurality of nanoribbons laterally spaced apart from the first plurality of nanoribbons; a dielectric fill (106) adjacent to the first sub-fin region and the second sub-fin region; a first gate layer (118a) around the first plurality of nanoribbons; a second gate layer (118b) around the second plurality of nanoribbons; and a gate cut (120) laterally between the first plurality of nanoribbons and the second plurality of nanoribbons and extending into the dielectric fill between the first sub-fin region and the second sub-fin region, the gate cut in contact with the first gate layer and the second gate layer, wherein the gate cut has a bottom surface above a bottom surface of the dielectric fill, wherein the gate cut has a height-to-width aspect ratio of 5:1 or greater.

Anmelder

Firma

Intel Corporation

Land

🇺🇸 USA