Verfahren und System zur Deterministischen Kommunikation zwischen mehreren Verbundenen Halbleiterchips
Anmelder: INTEL Corporation 🇺🇸
Details
- Veröffentlichungs-Nr.
- EP4752675
- Anmeldetag
- 28. Oktober 2025
- Veröffentlichung
- 3. Juni 2026
- Rechtsraum
- EP
- IPC
- G06F1/12, H04L47/28
Abstract
A method and system for deterministic communications between a plurality of interconnected semiconductor chips. The system includes a plurality of semiconductor chips, and a controller coupled to each of the plurality of semiconductor chips, respectively. The controller is configured to transfer data from one semiconductor chip to another. Each of the semiconductor chips and the controller include a respective clock, and the controller is configured to synchronize the clocks of the plurality of semiconductor chips. The controller schedules and manages data flows from and to the plurality of semiconductor chips for deterministic communications between the plurality of semiconductor chips. The controller may implement IEEE Time Sensitive Networking (TSN) protocol for scheduling and managing the data flows between the plurality of semiconductor chips.
Anmelder
- Firma
- INTEL Corporation
- Land
- 🇺🇸 USA
US-amerikanischer Halbleiterhersteller mit Sitz in Kalifornien. Entwickelt und produziert Prozessoren, Chipsätze sowie weitere Halbleiterkomponenten für Computer, Server und eingebettete Systeme.
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