Empfänger

Details

Veröffentlichungs-Nr.

EP4753201

Anmeldetag

28. November 2024

Veröffentlichung

3. Juni 2026

Rechtsraum

EP

IPC

H04L7/00, H04L7/033, H04L25/03

Abstract

A receiver for a wireline channel communication system, comprising an input for receiving a signal from one or more wires and an analog to digital configured to output a digital representation of the analog signal. A slicer module configured output a digital logic signal based on an amplitude of the analog signal. A high pass filter configured to receive the digital representation of the analog signal and output a filtered signal. A phase detector configured to receive a first signal based on the digital logic signal, and the filtered signal and configured to output an error signal indicative of a phase difference between the first signal and the filtered signal. A clock data recovery module configured to output a clock adjustment signal based on the error signal, wherein the clock adjustment signal is configured to control a sampling performed by the ADC.

Anmelder

Firma

NXP B.V.

Land

🇳🇱 Niederlande