Schmütz, Christian Klaus Johannes

A frame structure is described for aggregated data over a half-duplex serial data channel. In an example a serial link modem includes a transmit modem coupled to a serial channel and configured to send serial data through the serial channel, and an aggregator coupled to the transmit modem and configured to form a first frame type of serial data configured for data other than Universal Serial Bus (USB) data having an upstream packet and a downstream packet and a total length of less than a latency of two USB hubs, and a second frame type of serial data configured for USB data, wherein the aggregator forms the second frame type upon receiving USB data and wherein the transmit modem is configured to transmit the first frame type through the serial channel, and to transmit the second frame type through the serial channel upon completion of transmitting the first frame.

Embodiments of a repeater, an embedded Universal Serial Bus (eUSB) repeater, and a method of operating a repeater are disclosed. In an embodiment, a repeater includes a buffer configured to store data that is received during a time distance between an input start and a frame slot start, a counter configured to calculate a waiting time before starting frame transmission, and a transmitter configured to transmit predefined data at the frame slot start over a repeater channel and to transmit the data that is stored in the buffer over the repeater channel after the waiting time from the frame slot start.

Embodiments of a repeater (402), an embedded Universal Serial Bus (eUSB) repeater (402), and a method of operating a repeater (402) are disclosed. In an embodiment, a repeater (402) includes a timer (436) configured to generate a counter value that represents a time distance between a frame slot and a packet start and a modem (418) configured to transmit output data containing the counter value over a repeater channel (420).

An electronic circuit includes a fast-settling threshold estimator for determining a fast-settling threshold voltage which includes a maximum peak detector that receives an analog signal containing digital data and produces an estimate of a maximum value of the analog signal; a differentiator that produces an output voltage responsive to a change in the estimate of a maximum value of the analog signal; a preselected voltage coupled to a comparator that outputs a pulse when the output voltage is greater than the preselected voltage; a minimum peak detector that produces an estimate of a minimum value of the analog signal; and an averaging circuit that produces a weighted average of the estimate of a maximum value of the analog signal and the estimate of a minimum value of the analog signal. In one embodiment, the fast-settling threshold estimator is coupled to a bit slicer and to a RF receiver.

Systems and methods for an implicit frequency multiplier are described. In some embodiments, an implicit frequency multiplier may include a cross-coupled oscillator having a transistor pair, a primary coil coupled to source terminals of the transistor pair, and a secondary coil magnetically coupled to the primary coil. In another embodiment, a method may include operating a cross-coupled oscillator having a transistor pair and extracting a harmonic component of a current flowing through the cross-coupled oscillator using a transformer coupled to source terminals of the transistor pair.

Circuits and methods are disclosed that include a boost rail having a first voltage and an electrostatic discharge (ESD) rail having a second voltage that is less than the first voltage. An ESD protection circuit may include a trigger circuit configured to determine an ESD event on the boost rail and to selectively activate a clamp circuit to shunt current from the ESD rail to a power supply terminal in response to the ESD event. The circuit may include a first voltage drop circuit having a first configuration and coupled between a first power supply terminal and the boost rail to provide the first voltage and a second voltage drop circuit having a second configuration and coupled between the ESD rail and one of the boost rail or the first power supply terminal.

A USB-capable device includes an eUSB device repeater includes D+ and D- lines for communicating via a USB bus, and eD+ and eD- lines for communicating via an eUSB bus. The repeater includes a squelch detector for detecting a differential voltage between the D+ and D- lines and comparing it to a squelch threshold voltage based on a selectively variable squelch threshold voltage level at the squelch detector. During USB bus reset the squelch detector compares the differential voltage to a chirp-specific squelch threshold voltage level and the squelch signal indicates no K chirp or J chirp activity on the USB bus. The repeater thereby avoids false detections of invalid chirps and more reliably detects end of USB bus resets. A USB2 bus reset sequence windowing scheme is also provided.

This disclosure generally relates to an apparatus and a method for amplitude and duration comparison of an analog signal, in particular for analog signals with noise.

The present disclosure relates to an Ethernet device being configured to change stepwise from an idle state to a full active state, wherein the Ethernet device being configured to either detect a predefined signal during an arbitration cycle in order to perform a final step to fully activate the Ethernet device or otherwise to either maintain in an intermediate state or to change back to the idle state. The present disclosure also relates to a method for the Ethernet device.

A current mirror circuit (200) comprises: a first current source (206) for providing a first reference current (IB1); a first transistor (M1, 222) having a control terminal (226), a first current terminal (228) coupled to receive the first reference current (IB1), and a second current terminal (230) coupled to a reference potential (VEE); a second transistor (M2, 224) having a control terminal (232) coupled to the control terminal (226) of the first transistor (M1, 222), a first current terminal (234) coupled to an output node (GL, 208) of the current mirror circuit (200), and a second current terminal (236) coupled to the reference potential (VEE); and matching circuitry (300) having an input (302) coupled to the output node (GL, 208) of the current mirror circuit (200), and an output (304) coupled to the first current terminal (228) of the first transistor (M1, 222), the matching circuitry (300) being configured to provide, at the first current terminal (228) of the first transistor (M1, 222), a replica voltage corresponding to a voltage at the output node (GL, 208) of the current mirror circuit (200).