Verfahren und Vorrichtungen zur Implementierung einer Takterweiterung auf Basis eines Integrierten Schaltungsbusses Iic

Details

Veröffentlichungs-Nr.

EP4756631

Anmeldetag

27. Dezember 2024

Veröffentlichung

10. Juni 2026

Rechtsraum

EP

IPC

G06F13/42

Abstract

The present application provides methods and apparatuses for implementing clock extension based on an integrated circuit bus IIC. The present application additionally provides a clock extension indication signal line between an IIC master device and a control device in a communication control system. The IIC master device sends a first notification to the control device through the clock extension indication signal line to enable clock extension, so that the control device maintains a pin of a slave device SCL in a low-level state, to suspend data transmission. In the absence of a second notification sent by the IIC master device to the control device through the clock extension indication signal line to cancel clock extension, even if the specified period of the SCL clock cycle ends, the slave device SCL pin connected to the slave device SCL will not be controlled to be in a high impedance state as it would be in the conventional IIC data transmission mechanism. Instead, the SCL pin will be maintained at a low level until the second notification is received, breaking the limitation of the existing data transmission mechanism and implementing triggering of clock extension mechanism by the IIC master device.

Anmelder

Firma

New H3C Technologies Co., Ltd.

Land

🇨🇳 China

Fachgebiete