Halbleiteranordnung

Details

Veröffentlichungs-Nr.

EP4757534

Anmeldetag

6. Dezember 2024

Veröffentlichung

10. Juni 2026

Rechtsraum

EP

Abstract

In an aspect there is provided a semiconductor device comprising:a first and second power rail structure extending in parallel, each comprising a bottom power rail and a top power rail arranged above the bottom power rail;a row of local interconnects arranged between and extending in parallel to the first and second rows of CFET devices;a first and second row of complementary field-effect transistor, CFET, devices extending in parallel to the first and second power rail structures, wherein the first row of CFET devices is arranged between the first power rail structure and the row of local interconnects, and the second row of CFET devices is arranged between the second power rail structure and the row of local interconnects;a logic cell comprisingat least one CFET device of the first row of CFET devices configured to implement a first logic gate, and a first local interconnect of the row of local interconnects configured to interconnect a top and bottom source/drain, S/D, of a first CFET device of the at least one CFET device of the first row of CFET devices; andat least one CFET device of the second row of CFET devices configured to implement a second logic gate, and a second local interconnect of the row of local interconnects configured to interconnect a top and bottom S/D of a second CFET device of the at least one CFET device of the second row of CFET devices,wherein the first logic gate is connected to first input and output pins of the logic cell and the second logic gate is connected to second input and output pins of the logic cell, andwherein the first power rail structure is configured to power the first logic gate and the second power rail structure is configured to power the second logic gate.

Anmelder

Firma

IMEC vzw

Land

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