Diodenstruktur mit Benachbarten Basiszonen
Anmelder: INTEL Corporation 🇺🇸
Details
- Veröffentlichungs-Nr.
- EP4757535
- Anmeldetag
- 24. November 2025
- Veröffentlichung
- 10. Juni 2026
- Rechtsraum
- EP
- IPC
- H10D89/60
Abstract
Techniques for protecting integrated circuits from electrostatic discharge (ESD). A diode structure includes multiple emitter, base, and collector connections across a substrate. The connections are made to either n-doped substrate regions (for collector and emitter in NPN diode) or p-doped regions (for the base in NPN diode). P-doped base regions are arranged adjacent to each other in the substrate and are separated by a dielectric wall (e.g., shallow trench isolation). N-doped emitter regions may be arranged between sets of p-doped base regions. This arrangement effectively enlarges the base area of the diode structure, which decreases the current density. Additionally, the adjacent base regions allow for a wider metal interconnect layer over the adjacent base regions and a greater spacing between adjacent base and emitter interconnect layers. PNP diode structure is similarly configured, but with the dopant scheme reversed (p-doped substrate regions for collector and emitter and n-doped regions for base).
Anmelder
- Firma
- INTEL Corporation
- Land
- 🇺🇸 USA
US-amerikanischer Halbleiterhersteller mit Sitz in Kalifornien. Entwickelt und produziert Prozessoren, Chipsätze sowie weitere Halbleiterkomponenten für Computer, Server und eingebettete Systeme.
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