Privater 3D-Scratchpad-Speicher in einer Pipeline für Simt-Berechnungskerne

Details

Veröffentlichungs-Nr.

EP4764839

Anmeldetag

18. Dezember 2024

Veröffentlichung

24. Juni 2026

Rechtsraum

EP

Abstract

A processor core (1) of the SIMT type and a related method of operation are disclosed. The processor core comprises frontend circuitry (10), a plurality of lanes (20a-f), a multi-banked and arbitration-free scratchpad memory (40), and an interconnect (50) to couple active ones of the plurality of lanes to different ones of the scratchpad memory banks. There are at least as many banks as lanes in the processor core. Each lane comprises a thread-private register file (21a-f) and address generation logic (22a-f) to independently calculate an effective address of an operand within the scratchpad memory. An execution pipeline of the processor core, associated with the thread-parallel execution of vector memory instructions, comprises at least the address generation logic of the different lanes, the interconnect, and the different banks as pipeline components. The processor core is implemented as a stack of dies (2a, 2b) including the frontend circuitry and the plurality of lanes on a first die (2a) and the scratchpad memory on a second die (2b).

Anmelder

Firma

Imec VZW

Land

🇧🇪 Belgien