Konfigurierbares Datenfluss-Backend für Subwortparallelen Simt-Prozessor

Details

Veröffentlichungs-Nr.

EP4764840

Anmeldetag

19. Dezember 2024

Veröffentlichung

24. Juni 2026

Rechtsraum

EP

IPC

G06F9/30

Abstract

A Single Instruction Multiple Threads (SIMT) processor core comprising: (a) a configurable dataflow backend operative to support subword parallelism for execution of mixed-precision arithmetic operations, wherein the backend includes multiple dataflow network stages, each dataflow network stage including one or more functional units configurable to process multiple subwords within a register in parallel; (b) a configuration memory storing configuration data defining operational configurations of the dataflow network stages in the backend, wherein the configuration memory is accessible via a configuration index mechanism operative to select configuration data from the configuration memory to control the dataflow network stages in the backend, and wherein the configuration index mechanism is configured for enabling the dataflow backend to support multiple variations of mixed-precision arithmetic operations without requiring dedicated instructions for each variation.

Anmelder

Firma

Imec VZW

Land

🇧🇪 Belgien

Fachgebiete