Ausgekleideter Hohlraumabstandshalter für Gate-All-Around-Transistor

Details

Veröffentlichungs-Nr.

EP4766075

Anmeldetag

28. November 2025

Veröffentlichung

24. Juni 2026

Rechtsraum

EP

IPC

H10D30/00, // H10D30/01

Abstract

Described herein are nanoribbon transistors with lined cavity spacers deposited near the ends of the nanoribbons, including between the ends of adjacent nanoribbons. The cavity spacers include a liner layer next to the gate stack, and a fill material nested within the liner layer and adjacent to the source or drain. The liner layer is a non-oxide dielectric. For example, the liner may be a low-k nitride. The liner layer may be conformally deposited, and a portion of the liner layer may extend between the gate stack and the source or drain. Using a non-oxide material prevents removal of the liner during an oxide clean step prior to nanoribbon release.

Anmelder

Firma

INTEL Corporation

Land

🇺🇸 USA