Neuartige Ressourcenoptimierte Quellensynchrone Datenübertragung
Anmelder: NXP USA, Inc. 🇺🇸
Details
- Veröffentlichungs-Nr.
- EP4769164
- Anmeldetag
- 9. Dezember 2025
- Veröffentlichung
- 1. Juli 2026
- Rechtsraum
- EP
- IPC
- G06F13/42, G11C7/10
Abstract
An integrated circuit and associated method of operation are provided for a target component coupled over a bus having multiple data path lines and a clock path line to an initiator component which generates a plurality of data bit signals and a first clock timing signal for transmission in parallel over the bus, where the initiator component includes transmit circuitry to launch a first plurality of even data bit signals over a first subset of the plurality of data path lines in response to a rising clock edge of the first clock signal and to launch a second plurality of odd data bit signals over a second subset of the plurality of data path lines in response to a falling clock edge of the first clock signal.
Anmelder
- Firma
- NXP USA, Inc.
- Land
- 🇺🇸 USA
US-amerikanische Gesellschaft des Halbleiterkonzerns NXP, die Chips und Halbleiterlösungen für Automobiltechnik, Kommunikation und Industrieelektronik entwickelt.
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