Transistor-Source/drain-Barrieren zur Unterfinneentfernung

Details

Veröffentlichungs-Nr.

EP4770318

Anmeldetag

25. November 2025

Veröffentlichung

1. Juli 2026

Rechtsraum

EP

Abstract

Transistor structures with silicon source and drain semiconductor material that is protected from a backside silicon subfin material removal process by an intervening barrier material layer. A source/drain barrier material layer may comprise a crystalline material, such as SiGe, grown on the subfin prior to growth of the source/drain material. Optionally, a growth mask may be deposited over channel material before growing source/drain barrier material layer to avoid a heterojunction between channel and source/drain semiconductor materials. Alternatively, a source/drain barrier material layer may comprise an amorphous dielectric material deposited on the subfin prior to growth of the source/drain material. Following frontside processing, a workpiece may be inverted and subfin material removed selectively over the source/drain barrier material layer.

Anmelder

Firma

Intel Corporation

Land

🇺🇸 USA