Elektronisches Produkt, Zugehöriges Halbleiterprodukt und Verfahren zum Testen der Integrität eines Derartigen Elektronischen Produkts

Details

Veröffentlichungs-Nr.

EP4773174

Anmeldetag

2. Januar 2025

Veröffentlichung

8. Juli 2026

Rechtsraum

EP

IPC

H01L21/66

Abstract

The invention concerns a wafer comprising: - a metal layer deposited on a substrate, said metal layer comprising at least: • a first region made of said metal; and • a porous region comprising a plurality of substantially straight pores that extend from a top surface of the first porous region towards the substrate, the porous region being thicker than the first region; - at least one integrated device formed inside the pores of the porous region; the wafer further comprising: - a test arrangement comprising: • an insulating layer deposited on both the first region and the porous region, • a first contact pad and a second contact pad deposited on the insulating layer above the porous region; and a third contact pad deposited on the insulating layer above the first region.

Anmelder

Firma

Murata Manufacturing Co., Ltd.

Land

🇯🇵 Japan

Fachgebiete