Verteilte Berechnung in einem Paket mit Dram-Chips und Logischer Chip

Details

Veröffentlichungs-Nr.

EP4787373

Anmeldetag

21. Januar 2026

Veröffentlichung

5. August 2026

Rechtsraum

EP

IPC

G11C5/02, G11C7/10, G11C11/402

Abstract

A system and devices (100) are disclosed for implementing Compute with Memory Stack (CMS) semiconductor hardware (e.g., die, packages, etc.) with an architecture integrating memory and compute on a die, implementing shorter distance high-bandwidth communication between elements, and minimizing data traffic. A device (100) includes a first die (110), the first die (110) including a first compute component, a second compute component, a first set of Through Silicon Vias, TSVs, (152) associated with the first compute component and connecting stacked dies of the device (100), and a second set of TSVs (152) associated with the second compute component and connecting the stacked dies of the device (100). The device (100) includes a second die (115), stacked on the first die (110). The second die (115) may include a first memory bank module connected to the first compute component using the first set of TSVs (152), and a second memory bank module connected to the second compute component using the second set of TSVs (152).

Anmelder

Firma

Samsung Electronics Co., Ltd.

Land

🇰🇷 Südkorea

Fachgebiete