Halbleitergehäuse mit Speicherchips

Details

Veröffentlichungs-Nr.

EP4793775

Anmeldetag

6. November 2025

Veröffentlichung

19. August 2026

Rechtsraum

EP

IPC

G06F11/10

Abstract

A semiconductor package includes first data memory dies configured to share a first control bus and a first data bus, the first data memory dies belonging to different ranks, a first error correction memory die configured to share the first control bus with the first data memory dies and connected to a first error correction bus, second data memory dies configured to share a second control bus and a second data bus, second data memory dies belonging to different ranks, and a second error correction memory die configured to share the second control bus with the second data memory dies and connected to the second error correction bus.

Anmelder

Firma

SK hynix Inc.

Land

🇰🇷 Südkorea

Fachgebiete