Nichtflüchtige Speichervorrichtung mit Hoher E/a-Effizienz auf Basis eines Separaten Befehlsadressenprotokolls, Betriebsverfahren dafür und Speichervorrichtung damit

Details

Veröffentlichungs-Nr.

EP4793782

Anmeldetag

10. Februar 2026

Veröffentlichung

19. August 2026

Rechtsraum

EP

Abstract

A storage device includes a memory device including command and address pins, data pins, first control signal pin, memory blocks, and a transceiver transmitting or receiving data through the data pins and a memory controller transmitting a command and an address to the memory device through the command and address pins, transmitting and receiving data to and from the memory device through the data pins, and transmitting a first control signal to the memory device through the first control signal pin. The memory device transmits, in response to receiving a select chip enable packet received through the command and address pins, a second control signal in an activated state to at least one driving circuit that, in response to receiving the second control signal in an activated state, drives the transceiver transmitting and receiving data. The memory device then transmits or receives first data based on the select chip enable packet and the first control signal through the data pins.

Anmelder

Firma

Samsung Electronics Co., Ltd.

Land

🇰🇷 Südkorea