Verfahren zum Entwurf einer Integrierten Schaltung

Details

Veröffentlichungs-Nr.

EP4793814

Anmeldetag

18. Februar 2025

Veröffentlichung

19. August 2026

Rechtsraum

EP

Abstract

In an aspect there is provided a computer-implemented method for designing an IC comprising CFET devices. The method comprises obtaining a functional description of the integrated circuit, and generating, based on the functional description, a layout of the integrated circuit. The layout defines first and second cell rows extending in parallel in a horizontal direction of the layout, and having equal row heights in a vertical direction of the layout. Generating the layout comprises placing first and second cells of a standard cell library in the layout. Each cell has a cell height equal to the row height, and comprises first and second cell edges extending in parallel in the horizontal direction. Each cell further comprises at least one CFET device having an active pattern extending in the horizontal direction. Each cell further comprises at least one local interconnect (LI) disposed on the second cell edge and configured to connect to a top and/or bottom S/D of a CFET device of the cell. The first and second cells are placed in the first and second cell rows, respectively, such that: the first cell edge of the first cell aligns with a first row boundary, the first cell edge of the second cell aligns with a second row boundary, and the second cell edges of the first and second cells align with and abut each other along a third row boundary between the first and second cell rows. The placement of the first and second cells is constrained such that the local interconnects of the first and second cells do not overlap.

Anmelder

Firma

Imec VZW

Land

🇧🇪 Belgien