Nichtflüchtige Speicheranordnung mit Speicherzellenmatrix

Details

Veröffentlichungs-Nr.

EP4793949

Anmeldetag

12. Februar 2026

Veröffentlichung

19. August 2026

Rechtsraum

EP

IPC

G11C7/10, G11C16/08, G11C16/26

Abstract

A nonvolatile memory device includes a memory cell array including a plurality of planes, a page buffer circuit connected to the memory cell array through a plurality of bit lines, an input/output circuit connected to the page buffer circuit through a plurality of data lines, a control logic circuit controlling an operation for the planes in response to a command, a first command-address pad set electrically connected to the control logic circuit and receiving a first command, and a second command-address pad set electrically connected to the control logic circuit and receiving a second command. A time during which the first command is received overlaps with a time during which the second command is received.

Anmelder

Firma

Samsung Electronics Co., Ltd.

Land

🇰🇷 Südkorea

Fachgebiete