Halbleiteranordnung

Details

Veröffentlichungs-Nr.

EP4794475

Anmeldetag

1. Oktober 2025

Veröffentlichung

19. August 2026

Rechtsraum

EP

Abstract

A semiconductor device comprising: a substrate (110) includes a first surface (110a) and a second surface (110b) opposing each other; an epitaxial layer (131) positioned on the first surface (110a) of the substrate (110), including a gate trench (160), and the epitaxial layer (131) having a first conductivity type; a channel layer (300) positioned on the inner sidewall (160_s) of the gate trench (160) and having the first conductivity type; a gate electrode (150) positioned on the inner side surface of the channel layer (300); a gate insulating layer (140) positioned on the bottom surface of the gate trench (160), and between the channel layer (300) and the gate electrode (150); a source electrode (173) positioned on the epitaxial layer (131); and a drain electrode (175) positioned on the second surface (110b) of the substrate (110).

Anmelder

Firma

Samsung Electronics Co., Ltd.

Land

🇰🇷 Südkorea