Verfahren zur Herstellung eines Eingelassenen Gate-Anschlusses und Wafer mit dem Versenkten Gate-Anschluss und mit Verringerter Verwölbung

Details

Veröffentlichungs-Nr.

EP4794476

Anmeldetag

12. Februar 2026

Veröffentlichung

19. August 2026

Rechtsraum

EP

Abstract

The proposed solution is designed for IGBT and discrete devices with vertical gate; the proposed method includes: trench formation, including lithography and etching, in a wafer; oxidation to grow gate dielectric; polysilicon filling with a thin layer to form first gate conductive layer; a second dielectric deposition and recession to fill half of the trench from the bottom up to a fixed depth; trench filling with polysilicon to form a second gate conductive layer. The second dielectric can be chosen with a dedicated stress and a dedicated recession, to counterbalance the polysilicon stress and reduce wafer warpage.

Anmelder

Firma

STMicroelectronics International N.V.

Land

🇨🇭 Schweiz